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cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-08361 rev. *c revised june 5, 2017 MB39C014 1 ch dc/dc converter ic with pfm/pwm synchronous rectification description the MB39C014 is a current mode type 1-channel dc/dc converter ic built-in switch ing fet, synchronous rectification, and down conversion support. the device is integrat ed with a switching fet, o scillator, error amplifier, pw m control circuit, reference voltage source, and powergood circuit. external inductor and decoup ling capacitor are needed onl y for the external component. as combining with external parts enables a dc/dc converter with a compact and high load response characteristic, this is suitab le as the built-in power supply for such as mobile phone/pda, dvds, and hdds. features high efficiency : 96% (max) output current (dc/dc) : 800 ma (max) input voltage range : 2.5 v to 5.5 v operating frequency : 2.0/3.2 mhz (typ) no flyback diode needed low dropout operation : for 100% on duty built-in high-precision refere nce voltage generator : 1.20 v 2% consumption current in shutdo wn mode : 1 a or less built-in switching fet : p-ch mos 0.3 ? (typ) n-ch mos 0.2 ? (typ) high speed for input and load tran sient response in the current mode over temperature protection packaged in a compact package : son10 applications flash roms mp3 players electronic dictionary devices surveillance cameras portable gps navigators mobile phones etc.
document number: 002-08361 rev. *c page 2 of 32 MB39C014 contents description ............. ........................ ..................... ................... 1 features ..................... ..................... ..................... ................... 1 applications ........... ........................ ..................... ................... 1 contents ................. ........................ ..................... ................... 2 1. pin assignment .............. ............................ ...................... 3 2. pin descriptions .............................. .................. ............... 3 3. i/o pin equivalent circui t diagram ........... ...................... 4 4. block diagram ................ ............................ ...................... 5 4.1 current mode ............. ......................... ...................... 6 5. function of each block . ............................ ...................... 7 5.1 pwm logic control circu it .................. ...................... 7 5.2 iout comparator circui t ..................... ...................... 7 5.3 error amp phase compen sation circuit ................... 7 5.4 vref circuit. ...................... ......................... .............. 7 5.5 powergood circuit .... ........................ ................... 7 5.6 protection circuit ........ ......................... ...................... 8 6. absolute maximum ratings ...................... ...................... 9 7. recommended operating c onditions .......................... 10 8. electrical characteristics ........................... .................... 11 9. test circuit for me asuring typical operating characteristics .................... ......................... .................... 13 10. application notes ......... ............................ .................... 14 10.1 selection of components ........... ........................... 14 10.2 output voltage settin g ...................... .................... 15 10.3 about conversion effi ciency ............. .................... 15 10.4 power dissipation and heat considerations ......... 16 10.5 transient response . ......................... .................... 16 10.6 board layout, design example ......... .................... 17 10.7 layout example of ic sw components ................ 17 10.8 notes for circuit desi gn .................... .................... 17 11. example of standard operation characteristics ...... 18 12. application circuit exam ples .................. .................... 27 12.1 application circuit ex ample 1 ............ .................... 27 12.2 application circuit ex ample 2 ............ .................... 27 12.3 application circuit exam ple components list ....... 28 13. usage precautions .......... ......................... .................... 29 14. ordering information ....... ......................... .................... 29 15. rohs compliance informat ion ................ .................... 29 16. package dimension ......... ......................... .................... 30 document history .. ........................ ..................... ................. 31 sales, solutions, and legal in formation ........................... 32
document number: 002-08361 rev. *c page 3 of 32 MB39C014 1. pin assignment 2. pin descriptions pin no pin name i/o description 1 lx o inductor connection output pin. high impedance during shut down. 2 gnd ? ground pin. 3 ctl i control input pin. (l : shut down / h : normal operation) 4 vref o reference voltage output pin. 5 powergood o powergood circuit output pin. internally connected to an n- ch mos open drain circuit. 6 fsel i frequency switch pin. (l (open) : 2.0 mhz, h : 3.2 mhz) 7 vrefin i error amplifier (error amp) non-inverted input pin. 8 mode i use pin at l level or leave open. 9 out i output voltage feedback pin. 10 vdd ? power supply pin. (top view) (wnk010) powergood vref ctl gnd lx vdd out mode vrefin fsel 12345 109876
document number: 002-08361 rev. *c page 4 of 32 MB39C014 3. i/o pin equivalent circuit diagram ? ? gnd vdd gnd vdd lx vref power good ? gnd fsel ? gnd vdd ? mode ? gnd vdd ? ? gnd vdd ctl gnd vdd ? ? vrefin out ? ? * : esd protection device
document number: 002-08361 rev. *c page 5 of 32 MB39C014 4. block diagram vdd err 3 amplifier i out comparator 1.20 v v ref pwm logic control on/off ctl out powergood power good vref vrefin dac mode fsel gnd gnd lx v out vdd v in 10 3 9 5 4 7 8 ? + 6 2 1
document number: 002-08361 rev. *c page 6 of 32 MB39C014 4.1 current mode original voltage mode type: stabilize the output voltage by compar ing two items below and on-duty control. ? voltage (vc) obtained thro ugh negative feedback of the output voltage by error amp ? reference triangular wave (v tri ) current mode type: instead of the tr iangular wave (v tri ), the voltage (v idet ) obtained through i-v conversion of the sum of currents that flow in the oscillator (rectangular wa ve generation circuit) and sw fet is used. stabilize the output voltage by compar ing two items below and on-duty control. ? voltage (v c ) obtained through negative feedback of the output voltage by error amp ? voltage (v idet ) obtained through i-v conversion of the sum of current that fl ow in the oscillator (rectangu lar wave generation circuit) and sw fet v in ton toff v tri v c vc v tri v in toff vc vc v idet s r ton sr-ff v idet q voltage mode type model current mode type model oscillator note : the above models illustrate the gener al operation and an actual operat ion will be preferred in the ic.
document number: 002-08361 rev. *c page 7 of 32 MB39C014 5. function of each block 5.1 pwm logic control circuit the built-in p-ch and n-ch mos fets are controlled for synchronizatio n rectification according to the frequency (2.0 mhz/3.2 mh z) oscillated from the built- in oscillator (square wave oscillation circuit). 5.2 i out comparator circuit this circuit detects the current (i lx ) which flows to the external inducto r from the built-in p-ch mos fet. by comparing v idet obtained through i-v conv ersion of peak current i pk of i lx with the error amp output, th e built-in p-ch mos fet is turned off via the pwm logic control circuit. 5.3 error amp phase compensation circuit this circuit compares the output voltage to reference voltages such as vref. this ic has a built-in phase compensation circuit that is designed to optimize the operation of th is ic. this needs neither to be considered nor addition of a phase compensation cir cuit and an external phase compensation device. 5.4 vref circuit a high accuracy reference voltage is gener ated with bgr (bandgap reference) circui t. the output voltage is 1.20 v (typ). 5.5 powergood circuit the powergood circuit monitors the voltage at the out pin. the powergood pin is open drain output. use the pin with pull-up using the extern al resistor in th e normal operation. when the ctl is at the h level, the powergood pin becomes the h level. however, if the output voltage drops because of over current and etc, the powergood pin becomes the l level. timing chart example : (powerg ood pin pulled up to vin) vin ctl t dlypg or less t dlypg t dlypg vout p owergood (pull up to vin) v uvlo v out 97 % v uvlo : uvlo threshold voltage t dlypg : powergood delay time
document number: 002-08361 rev. *c page 8 of 32 MB39C014 5.6 protection circuit this ic has a built-in over-t emperature protection circuit. the over-temperature protection circuit turns off both n-ch and p-ch switching fets when the junction temperature reaches +135c. when the junction temperature comes down to + 110c, the switching fet is returned to the normal operation. since the pwm control circuit of this ic is in the control method in current mo de, the current peak valu e is also monitored and controlled as required. function table * : don't care mode input output switching frequency ctl fsel output pin voltage vref powergood shutdown mode ? l * output stop output stop function stop operation mode 2.0 mhz h l vout voltage output 1.2 v operation 3.2 mhz h h
document number: 002-08361 rev. *c page 9 of 32 MB39C014 6. absolute maximum ratings *1 : power dissipation value between + 25c and + 85c is obtained by connecting th ese two points with a straight line *2 : when mounted on a four- laye r epoxy board of 11.7 cm 8.4 cm *3 : connection at exposure pad with thermal via. (thermal via 4 holes) *4 : connection at exposure pad, without a thermal via. notes: the use of negative voltages below ? 0.3 v to the gnd pin may create parasitic trans istors on lsi lines, which can cause abnormal operation. this device can be damaged if the lx pin is short-circuited to vdd or gnd. take measures not to keep the fsel pin falling below the gnd potential of this ic as much as possible. in addition to erroneous operat ion, the ic may latch up and de stroy itself if 110 ma or more current flows from this pin. warning: semiconductor devices can be perma nently damaged by applicat ion of stress (voltage, cu rrent, temperature, etc.) in excess of absolute maximum rati ngs. do not exceed these ratings. parameter symbol condition rating unit min max power supply voltage v dd vdd pin ? 0.3 + 6.0 v signal input voltage v isig out pin ? 0.3 v dd + 0.3 v ctl, mode, fsel pins ? 0.3 v dd + 0.3 vrefin pin ? 0.3 v dd + 0.3 powergood pull-up voltage v ipg powergood pin ? 0.3 + 6.0 v lx voltage v lx lx pin ? 0.3 v dd + 0.3 v lx peak current i pk i lx ?1.8a power dissipation p d ta + 25c ? 2632* 1, * 2, * 3 mw ?980* 1, * 2, * 4 ta = + 85 c ? 1053* 1, * 2, * 3 mw ?392* 1, * 2, * 4 operating ambient temperature ta ? ? 40 + 85 c storage temperature t stg ? ? 55 + 125 c
document number: 002-08361 rev. *c page 10 of 32 MB39C014 7. recommended operating conditions note: the output current from this device has a situation to decr ease if the power supply voltage (v in ) and the dc/dc converter output voltage (v out ) differ only by a small amount. th is is a result of slope compensati on and will not damage this device. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device's electrical characteristics are warranted when the device is operat ed within these ranges. always use semiconductor devi ces within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinati ons not represented on the data sheet. users considering application outside the listed co nditions are advised to contact their representatives beforehand. parameter symbol condition value unit min typ max power supply voltage v dd ? 2.5 3.7 5.5 v vrefin voltage v refin ? 0.15 ? 1.20 v ctl voltage v ctl ?0?5.0v lx current i lx ???800ma powergood current i pg ???1ma vref output current i rout 2.5 v v dd 3.0 v ? ? 0.5 ma 3.0 v v dd 5.5 v ? ? 1 inductor value l 2.0 mhz (fsel = l) ? 2.2 ? h 3.2 mhz (fsel = h) ? 1.5 ?
document number: 002-08361 rev. *c page 11 of 32 MB39C014 8. electrical characteristics (ta = + 25c, vdd = 3.7 v, vout setting value = 2.5 v, mode = 0 v) * : standard design value parameter symbol pin no. condition value unit min typ max dc/dc converter block input current i refin m 7 v refin = 0.833 v ? 100 0 + 100 na i refin lv refin = 0.15 v ? 100 0 + 100 na i refin hv refin = 1.20 v ? 100 0 + 100 na output voltage v out 9 v refin = 0.833 v, out = ? 100 ma 2.45 2.50 2.55 v input stability line 2.5 v v dd 5.5 v * 1 ?10?mv load stability load ? 100 ma out ? 800 ma ? 10 ? mv out pin input impedance r out out = 2.0 v 0.6 1.0 1.5 m ? lx peak current i pk 1 output shorted to gnd 0.9 1.2 1.7 a oscillation frequency f osc1 fsel = 0 v 1.6 2.0 2.4 mhz f osc2 fsel = 3.7 v 2.56 3.20 3.84 mhz rise delay time t pg 3, 9 c1 = 4.7 f, out = 0 a, vout = 90% ?4580 s sw nmos fet off voltage v noff 1 ? ? 40* ? 20* 0* mv sw pmos fet on resistance r onp lx = ? 100 ma ? 0.30 0.47 ? sw nmos fet on resistance r onn lx = ? 100 ma ? 0.20 0.36 ? lx leak current i leak m0 lx v dd * 2 ? 1.0 ? + 8.0 a i leak hv dd = 5.5 v, 0 lx v dd * 2 ? 2.0 ? + 16.0 a protection circuit block over temperature protection (junction temp.) t otph ?? + 120* + 135* + 155* c t otpl + 95* + 110* + 130* c uvlo threshold voltage v thh 10 ? 2.07 2.20 2.33 v v thl 1.92 2.05 2.18 v uvlo hysteresis width v hys ? 0.080.150.25 v
document number: 002-08361 rev. *c page 12 of 32 MB39C014 (ta = + 25c, vdd = 3.7 v, vout setting value = 2.5 v, mode = 0 v) *1 : the minimum value of v dd is the 2.5 v or v out setting value + 0.6 v, whichever is higher. *2 : the + leak at the lx pin includes the current of the internal circuit. *3 : detected with respect to th e output voltage setting value of v refin *4 : current consumption based on 100% on-duty (high side fet in full on state). the sw fet ga te drive current is not included because the de vice is in full on state (no switching operation). also t he load current is not included. parameter symbol pin no. condition value unit min typ max power good block powergood threshold voltage v thpg 5 *3 v refin 3 0.93 v refin 3 0.97 v refin 3 0.99 v powergood delay time t dlypg1 fsel = 0 v ? 250 ? s t dlypg2 fsel = 3.7 v ? 170 ? s powergood output voltage v ol powergood = 250 a? ? 0.1v powergood output current i oh powergood = 5.5 v ? ? 1.0 a control block ctl threshold voltage v thhct 3 ? 0.55 0.95 1.45 v v thlct ? 0.40 0.80 1.30 ctl pin input current i ictl ctl = 3.7 v ? ? 1.0 a fsel threshold voltage v thhfs 6 ?2.96?? v v thlfs ???0.74 reference voltage block vref voltage v ref 4 vref = ? 2.7 a, out = ? 100 ma 1.176 1.200 1.224 v vref load stability l oadref vref = ? 1.0 ma ? ? 20 mv general shut down power supply current i vdd1 10 ctl = 0 v, all circuits in off state ??1.0 a i vdd1h ctl = 0 v, vdd = 5.5 v ? ? 1.0 a standby power supply current (dc/dc) i vdd2 ctl = 3.7 v, out = 0 a, fsel = 0 v ?4.08.0ma power-on invalid current i vdd ctl = 3.7 v, vout = 90%* 4 ? 800 1500 a
document number: 002-08361 rev. *c page 13 of 32 MB39C014 9. test circuit for measuring typical operating characteristics note : these components are recommended base d on the operating tests authorized. tdk : tdk corporation ssm : susumu co., ltd koa : koa corporation component specification vendor part number remark r1 1 m ? koa rk73g1jttd d 1 m ? r3-1 r3-2 7.5 k ? 120 k ? ssm ssm rr0816-752-d rr0816-124-d at vout = 2.5 v setting r4 300 k ? ssm rr0816-304-d r5 1 m ? koa rk73g1jttd d 1 m ? c1 4.7 f tdk c2012jb1a475k c2 4.7 f tdk c2012jb1a475k c6 0.1 f tdk c1608jb1h104k for adjusting slow start time l1 2.2 h tdk vlf4012at-2r2m 2.0 mhz operation 1.5 h tdk vlf4012at-1r5m 3.2 mhz operation vin vout l1 c1 i ou t c2 sw ctl mode vref vrefin gnd out lx vdd gnd r5 v dd v dd MB39C014 power good fsel r1 r4 r3-1 r3-2 sw sw c6 10 3 8 4 6 7 1 9 5 2 output voltage = vrefin 2.97
document number: 002-08361 rev. *c page 14 of 32 MB39C014 10. application notes 10.1 selection of components 10.1.1 selection of an external inductor basically it dose not need to design induct or. this ic is designed to operate effici ently with a 2.2 h (2 .0 mhz operation) or 1.5 h (3.2 mhz operation) inductor. the inductor should be rated for a saturati on current higher than the lx peak curr ent value during normal operating conditions, and should have a minimal dc resistance. (100 m ? or less is recommended.) lx peak current value i pk is obtained by the following formula. l : external inductor value i out : load current v in : power supply voltage v out : output setting voltage d : on- duty to be switched( = v out /v in ) fosc : switching frequency (2.0 mhz or 3.2 mhz) ex) at v in = 3.7 v, v out = 2.5 v, i out = 0.8 a, l = 2.2 h, fosc = 2.0 mhz the maximum peak current value i pk ; 10.1.2 i/o capacitor selection select a low equivalent series resistanc e (esr) for the vdd input capacitor to su ppress dissipation from ripple currents. also select a low equivalent series resist ance (esr) for the output capacitor. the vari ation in the inductor current causes rip ple currents on the output capacitor which, in turn, causes ripple voltages an output equal to the amount of variation multiplied b y the esr value. the output capacitor value has a significant impact on the op erating stability of the device when used as a dc/dc converter. therefore, cypress generally recommends a 4.7 f capa citor, or a larger capacitor va lue can be used if ripple voltag es are not suitable. if the v in /v out voltage difference is within 0.6 v, the use of a 10 f output capacit or value is recommended. types of capacitors ceramic capacitors are effective for reducing the esr and afford smaller dc/dc converte r circuit. however, power supply functio ns as a heat generator, therefore avoid to us e capacitor with the f-temperature rating ( ? 80% to + 20%). cypress recommends capacitors with the b-temperature rating ( 10% to 20%). normal electrolytic capacitors are no t recommended due to their high esr. tantalum capacitor will reduce esr, however, it is dangerous to use because it turns into short mode when da maged. if you insis t on using a tantalum capacitor, cypress re commends the type with an internal fuse. i pk = i out + v in ? v out d 1 = i out + (v in ? v out ) v out l fosc 2 2 l fosc v in i pk = i out + (v in ? v out ) v out = 0.8 a + (3.7 v ? 2.5 v) 2.5 v := 0.89 a 2 l fosc v in 2 2.2 h 2 mhz 3.7 v
document number: 002-08361 rev. *c page 15 of 32 MB39C014 10.2 output voltage setting the output voltage v out of this ic is defined by the voltage input to vrefin . supply the voltage for inpu tting to vrefin from an external power supply, or set the vref output by dividing it with resistors. the output voltage when the vref in voltage is set by dividing th e vref voltage with resistors is shown in the following formula . note : refer to ? application circuit examples ? for an example of this circuit. although the output voltage is de fined according to the dividing ratio of resistance, select the resistance value so that the c urrent flowing through the resistance does not e xceed the vref current rating (1 ma) . 10.3 about conversion efficiency the conversion efficiency can be improved by reducing the loss of the dc/dc converter circuit. the total loss (p loss ) of the dc/dc converter is r oughly divided as follows : p loss = p cont + p sw + p c p cont : control system circuit loss (the power used for this ic to operate, including the gate driving power for internal sw fets) p sw : switching loss (the loss ca used during switching of th e ic's internal sw fets) p c : continuity loss (the loss caused wh en currents flow through the ic's inte rnal sw fets and external circuits ) the ic's control circuit loss (p cont ) is extremely small, less t han 100 mw with no load. as the ic contains fets which can switch fa ster with less power, the continuity loss (p c ) is more predominant as the loss during heavy- load operation than the control circuit loss (p cont ) and switching loss (p sw ) . v out = 2.97 v refin , v refin = r4 v ref r3 + r4 (v ref = 1.20 v) r4 r3 vref vrefin vref vrefin MB39C014 4 7
document number: 002-08361 rev. *c page 16 of 32 MB39C014 furthermore, the continuity loss (p c ) is divided roughly into the loss by internal sw fet on-resistance and by external inductor series resistance. p c = i out 2 (rdc + d r onp + (1 ? d) r onn ) d : switching on-duty cycle ( = v out / v in ) r onp : internal p-ch sw fet on resistance r onn : internal n-ch sw fet on resistance rdc : external inductor series resistance i out : load current the above formula indicates that it is impo rtant to reduce rdc as much as possible to improve effi ciency by selecting component s. 10.4 power dissipation and heat considerations the ic is so efficient that no consideratio n is required in most of th e cases. however, if the ic is used at a low power supply voltage, heavy load, high output volt age, or high temperature, it requires fu rther consideration for higher efficiency. the internal loss (p) is roughly obtained from th e following formula : p = i out 2 (d r onp + (1 ? d) r onn ) d : switching on-duty cycle ( = v out / v in ) r onp : internal p-ch sw fet on resistance r onn : internal n-ch sw fet on resistance i out : output current the loss expressed by the above formula is mainly continuity lo ss. the internal loss includes the switching loss and the contro l circuit loss as well but they are so small compared to the contin uity loss they can be ignored. in this ic with r onp greater than r onn , the larger the on-duty cycle, the greater the loss. when assuming v in = 3.7 v, ta = + 70c for example, r onp = 0.42 ? and r onn = 0.36 ? according to the graph ?mos fet on resistance vs. operating ambient temperature? . the ic's internal loss p is 144 mw at v out = 2.5 v and i out = 0.6 a. according to the graph ?power dissipation vs. operating ambien t temperature?, the power dissipation at an operating ambient temperature ta of + 70c is 539 mw and the internal loss is smaller than th e power dissipation. 10.5 transient response normally, i out is suddenly changed while v in and v out are maintained constant, responsive ness including the response time and overshoot/undershoot voltage is checked. as this ic has built-in error amp with an optimized design, it shows good transient re sponse characteristics. however, if ringing upon sudden change of the load is high due to the operating conditions, add capacitor c6 ( e.g. 0.1 f). (since this capacitor c6 changes th e start time, check the start waveform as we ll.) this action is not required for dac in put. r4 c6 r3 vref vrefin vref vrefin MB39C014 4 7
document number: 002-08361 rev. *c page 17 of 32 MB39C014 10.6 board layout, design example the board layout needs to be designed to ensure the stab le operation of this ic. follow the procedure below for designing the layout. arrange the input capacitor (cin) as close as possible to both the vdd and gnd pins. ma ke a thru-hole (th) near the pins of thi s capacitor if the board has planes for power and gnd. large ac currents flow between this ic and the input capacitor (cin ), output capacitor (c o ), and external inductor (l). group these components as close as possible to this ic to reduce the overall loop area occupied by this group. also try to mount these com ponents on the same surface and arrange wi ring without thru-hole wiring. use thick, short, and straight routes to wire the net (the lay out by planes is recommended.). the feedback wiring to the out should be wired from the voltage output pi n closest to the output capacitor (c o ). the out pin is extremely sensitive and should thus be kept wired away from the lx pin of this ic as far as possible. if applying voltage to the vrefin pin thro ugh dividing resistors, arrange the resistor s so that the wiring ca n be kept as short as possible. also arrange them so that the gn d pin of the vrefin resistor is close to the ic's gnd pin. further, provide a gnd exclusively for the control line so that t he resistor can be connected vi a a path that does not carr y current. if installing a bypass capacitor for the vrefin, put it close to the vrefin pin. try to make a gnd plane on the surface to which this ic will be mounted. for efficient heat dissipation when using the son-10 package, cypress recommends providing a therma l via in the footprin t of the thermal pad. 10.7 layout example of ic sw components 10.8 notes for circuit design the switching operation of this ic works by monitoring and contro lling the peak current which, in cidentally, serves as form of short- circuit protection. however, do not leave the output short-circuited for long periods of time. if the output is short-circuited where vin < 2.9 v, the current limit value (peak current to the inductor) te nds to rise. leaving in the short-circuit state, the temperat ure of this ic will continue rising and ac tivate the thermal protection. once the thermal protection stop s the output, the temperature of the ic will go down and operat ion will resume, after which the output will repeat the starting and stopping. although this effect will not destroy the ic , the thermal exposure to the ic over pr olonged hours may affect the peripherals su rrounding it. co cin vo l gnd 1 pin vin feedback line
document number: 002-08361 rev. *c page 18 of 32 MB39C014 11. example of standard operation characteristics (shown below is an example of charac teristics for connection according to? test circuit for measuring typical operating characteristics ?). 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 v in = 3.7 v v in = 4.2 v v in = 3.0 v ta = + 25 c v out = 2.5 v fsel = l v in = 5.0 v 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 ta = + 25 c v out = 1.2 v fsel = l v in = 3.7 v v in = 3.0 v v in = 4.2 v v in = 5.0 v ta = + 25 c v out = 1.8 v fsel = l 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 v in = 3.7 v v in = 3.0 v v in = 4.2 v v in = 5.0 v ta = + 25 c v out = 3.3 v fsel = l 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 v in = 3.7 v v in = 4.2 v v in = 5.0 v load current i out (ma) conversion efficiency (%) load current i out (ma) conversion efficiency (%) load current i out (ma) conversion efficiency (%) load current i out (ma) conversion efficiency (%) conversion efficiency vs. load current (2.0 mhz) conversion efficiency vs. load current (2.0 mhz) conversion efficiency vs. load current (2.0 mhz) conversion efficiency vs. load current (2.0 mhz)
document number: 002-08361 rev. *c page 19 of 32 MB39C014 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 0 v in = 3.7 v v in = 3.0 v v in = 4.2 v v in = 5.0 v ta = + 25 c v out = 2.5 v fsel = h 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 0 v in = 3.7 v v in = 3.0 v v in = 4.2 v v in = 5.0 v ta = + 25 c v out = 1.2 v fsel = h 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 0 v in = 3.7 v v in = 3.0 v v in = 4.2 v v in = 5.0 v ta = + 25 c v out = 1.8 v fsel = h 10 20 30 40 50 60 70 80 90 100 1 10 100 100 0 0 v in = 4.2 v v in = 5.0 v ta = + 25 c v out = 3.3 v fsel = h v in = 3.7 v load current i out (ma) conversion efficiency (%) load current i out (ma) conversion efficiency (%) load current i out (ma) conversion efficiency (%) load current i out (ma) conversion efficiency (%) conversion efficiency vs. load current (3.2 mhz) conversion efficiency vs. load current (3.2 mhz) conversion efficiency vs. load current (3.2 mhz) conversion efficiency vs. load current (3.2 mhz)
document number: 002-08361 rev. *c page 20 of 32 MB39C014 2.40 2.0 3.0 4.0 5.0 6.0 2.42 2.44 2.46 2.48 2.50 2.52 2.54 2.56 2.58 2.60 i out = 0 a i out = 100 ma 2.40 2.0 3.0 4.0 5.0 6.0 2.42 2.44 2.46 2.48 2.50 2.52 2.54 2.56 2.58 2.60 i out = 0 a i out = 100 ma 0 200 400 600 800 2.40 2.42 2.44 2.46 2.48 2.50 2.52 2.54 2.56 2.58 2.60 0 200 400 600 800 2 .40 2 .42 2 .44 2 .46 2 .48 2 .50 2 .52 2 .54 2 .56 2 .58 2.60 input voltage v in (v) output voltage v out (v) input voltage v in (v) output voltage v out (v) load current i out (ma) output voltage v out (v) load current i out (ma) output voltage v out (v) output voltage vs. input voltage (2.0 mhz) output voltage vs. input voltage (3.2 mhz) output voltage vs. load current (2.0 mhz) output voltage vs. load current (3.2 mhz) ta = + 25c v out = 2.5 v setting fsel = l ta = + 25c v out = 2.5 v setting fsel = h ta = + 25c v in = 3.7 v v out = 2.5 v setting fsel = l ta = + 25c v in = 3.7 v v out = 2.5 v setting fsel = h
document number: 002-08361 rev. *c page 21 of 32 MB39C014 1.1 23456 1.12 1.14 1.16 1.18 1.2 1.22 1.24 1.26 1.28 1.3 ta = + 25 c v out = 2.5 v v in = 3.7 v v out = 2.5 v 1.1 1.12 1.14 1.16 1.18 1.2 1.22 1.24 1.26 1.28 1.3 ? 50 0 +50 +100 0 2.0 3.0 4.0 5.0 6.0 1 2 3 4 5 6 7 8 9 10 ta = + 25 c v out = 2.5 v 0 ? 50 0 +50 +100 1 2 3 4 5 6 7 8 9 10 v in = 3.7 v v out = 2.5 v reference voltage vs. input voltage reference voltage v ref (v) input current vs. operating ambient temperature input current i in (ma) input current vs. input voltage input current i in (ma) reference voltage vs. operating ambient temperature reference voltage v ref (v) input voltage v in (v) operating ambient temperature ta (c) input voltage v in (v) operating ambient temperature ta (c)
document number: 002-08361 rev. *c page 22 of 32 MB39C014 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.0 3.0 4.0 5.0 6.0 ta = + 25 c i out = 200 ma v out = 2.5 v fsel = l 2.4 2.6 2.8 3.0 3.2 3.4 3.6 2.0 3.0 4.0 5.0 6.0 ta = + 25 c i out = 200 ma v out = 2.5 v fsel = h 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 ? 50 0 +50 +100 v in = 3.7 v i out = 200 ma v out = 2.5 v fsel = l 2.4 2.6 2.8 3.0 3.2 3.4 3.6 ? 50 0 +50 +100 v in = 3.7 v i out = 200 ma v out = 2.5 v fsel = h input voltage v in (v) oscillation frequency f osc 1 (mhz) input voltage v in (v) oscillation frequency f osc 2 (mhz) operating ambient temperature ta (c) oscillation frequency f osc 1 (mhz) operating ambient temperature ta (c) oscillation frequency f osc 2 (mhz) oscillation frequency vs. input voltage (2.0 mhz) oscillation frequency vs. input voltage (3.2 mhz) oscillation frequency vs. operating am- bient temperature (2.0 mhz) oscillation frequency vs. operating ambient temperature (3.2 mhz)
document number: 002-08361 rev. *c page 23 of 32 MB39C014 0.0 0.1 0.2 0.3 0.4 0.5 0.6 2.0 3.0 4.0 5.0 6.0 p-ch n-ch ta = + 25 c 0.0 0.1 0.2 0.3 0.4 0.5 0.6 ? 50 0 +50 +100 v in = 3.7 v v in = 5.5 v 0.0 0.1 0.2 0.3 0.4 0.5 0.6 ? 50 0 +50 +100 v in = 5.5 v v in = 3.7 v 0.0 0.4 0.2 0.6 0.8 1.0 1.2 1.4 2.0 3.0 4.0 5.0 6.0 ta = + 25 c v thhct v thlct v out = 2.5 v input voltage v in (v) mos fet on resistance r on ( ? ) operating ambient temperature ta (c) p-ch mos fet on resistance r onp ( ? ) operating ambient temperature ta (c) n-ch mos fet on resistance r onn ( ? ) input voltage v in (v) ctl threshold voltage v th (v) mos fet on resistance vs. input voltage p-ch mos fet on resistance vs. operating ambient temperature n-ch mos fet on resistance vs. operating ambient temperature ctl threshold voltage v th vs. input voltage v thhct : off ? on v thlct : on ? off
document number: 002-08361 rev. *c page 24 of 32 MB39C014 switching waveforms 500 0 1000 1500 2000 2500 3000 ? 50 0 +50 +100 2632 +85 1053 500 0 1000 1500 2000 2500 3000 ? 50 0 +50 +100 980 +85 392 operating ambient temperature ta (c) power dissipation p d (mw) operating ambient temperature ta (c) power dissipation p d (mw) power dissipation vs. operating ambient temperature (with thermal via) power dissipation vs. operating ambient temperature (without thermal via) i lx : 500 ma/div v lx : 2.0 v/div v out : 20 mv/div ta = + 25 c v in = 3.7 v v out = 2.5 v i out = 800 ma 1 s/div
document number: 002-08361 rev. *c page 25 of 32 MB39C014 startup waveform v ctl : 5.0 v/div i lx : 500 ma/div v out : 1.0 v/div 10 ms/div ta = + 25 c v in = 3.7 v v out = 2.5 v i out = 0 a vrefin capacitor value = 0.1 f ta = + 25 c v in = 3.7 v v out = 2.5 v i out = 0 a v ctl : 2.0 v/div i lx : 500 ma/div v out : 1.0 v/div 20 s/div no vrefin capacitor
document number: 002-08361 rev. *c page 26 of 32 MB39C014 output waveforms at sudd en load changes (0 ma ? 800 ma) output waveforms at sudd en load changes (100 ma ? 800 ma) ta = + 25 c v in = 3.7 v v out = 2.5 v 10 s/div v out : 100 mv/div i out = 0 ma i out = 800 ma i out = 0 ma vrefin capacitor value = 0.1 f ta = + 25c v in = 3.7 v v out = 2.5 v i out = 100 ma i out = 800 ma i out = 100 ma v out : 100 mv/div 10 s/div vrefin capacitor value = 0.1 f
document number: 002-08361 rev. *c page 27 of 32 MB39C014 12. application circuit examples 12.1 application circuit example 1 an external voltage is input to the reference voltage extern al input (vrefin) , and the v out voltage is set to 2.97 times the v out setting gain. 12.2 application circuit example 2 the voltage of vref pin is input to th e reference voltage external input (vrefi n) by the dividing resistors. the v out voltage is set to 2.5 v. v out = 2.97 v refin v in cpu v out apli c2 c1 l1 r5 dac 4.7 f 4.7 f 2.2 h 1 m vdd ctl fsel vref vrefin gnd lx out power good mode l ( open ) = 2.0 mhz h = 3.2 mhz 10 3 8 5 9 1 6 4 7 2 v out = 2.97 v refin v out = 2.97 ( v ref = 1.20 v ) v refin = r4 r3 + r4 r4 300 k vdd ctl fsel vref vrefin gnd lx out power good mode 10 3 8 5 9 1 6 4 7 2 l ( open ) = 2.0 mhz r3 127.5 k h = 3.2 mhz v out apli c1 l1 4.7 f 2.2 h ( 120 k + 7.5 k ) cpu r5 1 m v in c2 4.7 f v ref 1.20 v = 2.5 v 300 k 127.5 k + 300 k
document number: 002-08361 rev. *c page 28 of 32 MB39C014 12.3 application circuit example components list tdk : tdk corporation fdk : fdk corporation koa : koa corporation component item part number specification package vendor l1 inductor vlf4012at-2r2m 2.2 h, rdc = 76 m ? smd tdk mipw3226d2r2m 2.2 h, rdc = 100 m ? smd fdk c1 ceramic capacitor c2012jb1a475k 4.7 f (10 v) 2012 tdk c2 ceramic capacitor c2012jb1a475k 4.7 f (10 v) 2012 tdk r3 resistor rk73g1jttd d 7.5 k ? rk73g1jttd d 120 k ? 7.5 k ? 120 k ? 1608 1608 koa r4 resistor rk73g1jttd d 300 k ? 300 k ? 1608 koa r5 resistor rk73g1jttd d 1 m ? 0.5% 1608 koa
document number: 002-08361 rev. *c page 29 of 32 MB39C014 13. usage precautions 1. do not configure the ic over the maximum ratings lf the lc is used over the maximum rati ngs, the lsl may be permanently damaged. it is preferable for the device to normall y operate within the recommended usage cond itions. usage outside of these conditions can adversely affect reli ability of the lsi. 2. use the devices within recommended operating conditions the recommended operating conditions are the conditions under which th e lsl is guaranteed to operate. the electrical ratings are guaran teed when the device is used wit hin the recommended operating co nditions and under the conditi ons stated for each item. 3. printed circuit board ground lines should be se t up with consideration for common impedance 4. take appropriate static electricity measures. containers for semiconductor material s should have anti-static protection or be made of conductive material. after mounting, printed circuit boards should be stored and shipped in conductive bags or containers. work platforms, tools, and instrume nts should be properly grounded. working personnel should be grou nded with resistance of 250 k ? to 1 m ? between body and ground. 5. do not apply negative voltages. the use of negative voltages below ? 0.3 v may create parasitic transist ors on lsi lines, which can cause abnormal operation. 14. ordering information 15. rohs compliance information the lsi products of cypress with ?e1? are compliant with rohs directive, and ha s observed the standard of lead, cadmium, mercur y, hexavalent chromium, polybromina ted biphenyls (pbb), and polybrom inated diphenylethers (pbde). a product whose part number has trailing characters ?e1? is rohs compliant. part number package remarks MB39C014pn- ??? e1 10-pin plastic son (wnk010) ?
document number: 002-08361 rev. *c page 30 of 32 MB39C014 16. package dimension millimeter nom. min. b e 2.40 bsc 3.00 bsc d a 1 a 3.00 bsc 0.00 symbol max. 0.75 0.05 0.50 bsc l 0.22 0.25 0.28 e d 2 2 1.70 bsc e c 0.30 ref 0.40 0.30 0.50 2. dimensioning and tolerancinc conforms to asme y14.5-1994. 3. n is the total number of terminals. 4. dimension "b" applies to metallized terminal and is measured between 0.15 and 0.30mm from terminal tip.if the terminal has the optional radius on the other end of the terminal. the dimension "b"should not be measured in that radius area. 5. nd refer to the number of terminals on d or e side. 6. max. package warpage is 0.05mm. 1. all dimensions are in millimeters. 7. maximum allowable burrs is 0.076mm in all directions. 8. pin #1 id on top will be located within indicated zone. 9. bilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals. note 10. jedec specification no. ref : n/a side view bottom view top view d a e b 0.10 c 2x 0.10 c 2x 0.10 c a a1 0.05 c c seating plane d2 e2 0.10 c a b 0.10 c a b 10 e b 0.10 c a b 0.05 c (nd-1) e index mark 8 4 5 9 l 9 6 1 5 package code: wnk010 002-15676 rev. **
document number: 002-08361 rev. *c page 31 of 32 MB39C014 document history document title: MB39C014 1 ch dc/dc conver ter ic with pfm/pwm synchronous rectification document number: 002-08361 revision ecn orig. of change submission date description of change ** ? taoa 11/21/2008 migrated to cypress and assigned document number 002-08361. no change to document contents or format. *a 5490964 taoa 10/24/2016 updated to cypress template. *b 5633455 hixt 02/17/2017 updated pin assignment : change the package name from lcc-10p-m04 to wnk010 updated ordering information : change the package name from lcc-10p-m04 to wnk010 deleted the words, ?lead free version?, in the remarks. deleted ?marking format (lead free version)? deleted ?labeling sample (lead free version)? deleted ?evaluation board specification? deleted ?ev board ordering information? updated package dimension : updated to cypress format *c 5761100 masg 06/05/2017 adapted cypress new logo.
document number: 002-08361 rev. *c revised june 5, 2017 page 32 of 32 ? cypress semiconductor corporation, 2008-2017. this document is the property of cypre ss semiconductor corporation and its subs idiaries, including spansion llc (?cypress?). this document, including any software or firmwa re included or referenced in this document (?software?), is owne d by cypress under the intellec tual property laws and treaties of th e united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragr aph, grant any license under its patent s, copyrights, trad emarks, or other intellectual property right s. if the software is not accomp anied by a license agreement and yo u do not otherwise have a writte n agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (witho ut the right to sublicense) (1) under its copyright rights in the software (a) for softwa re provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only internally within your organization, and (b) to distribute the software in bi nary code form externally to end users (either directly or indirectly through rese llers and distributors), solely for use on cy press hardware produc t units, and (2) u nder those claims of cypress?s patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import t he software solely for use with cypress hardware product s. any other use, reproduction, modi fication, translati on, or compilation of the software is prohibited. to the extent permitted by applicab le law, cypress makes no warrant y of any kind, express or implie d, with regard to this docum ent or any software or accompanying hardware, includ ing, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypr ess reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the applicati on or use of any product or circuit described in this document. any informati on provided in this document, incl uding any sample design informat ion or programming code, is provided only for reference purposes. it is the responsibility of the user of this docum ent to properly design, prog ram, and test the functional ity and safety of any appli cation made of this information and any resulting product. cypress products are not designed, inte nded, or authorized for use as critical components in systems designe d or intended for the operation of w eapons, weapons systems, nuclear instal lations, life-support devices or systems, other medical devices or systems (inc luding resuscitation equipment and surgical implants), pollution control or hazar dous substances management , or other uses wher e the failure of the device or system could cause per sonal injury, death, or property damage (?uninte nded uses?). a critical component is any compo nent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. cypress is not liable, in who le or in part, and you shall and hereby do release cypre ss from any claim, damage, or other liability arisi ng from or related to all unin tended uses of cypress products. you shall indemnify and hold cy press harmless from and against all claims, costs, damages, and other liabilities, including claims for pe rsonal injury or death, arising from or related to any un intended uses of cypress products. cypress, the cypress logo, spansion, the spansion l ogo, and combinations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tra veo are trademarks or regist ered trademarks of cypress in the united states and other countries. for a more complete li st of cypress trademar ks, visit cypress.com. other names and bra nds may be claimed as property of their respective owners. MB39C014 sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface internet of things cypress.com/iot memory cypress.com/memory microcontrollers cypress.com/mcu psoc cypress.com/psoc power management ics cypress.com/pmic touch sensing cypress.com/touch usb controllers cypress.com/usb wireless/rf cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp | psoc 6 cypress developer community forums | wiced iot forums | proj ects | video | blogs | training | components technical support cypress.com/support

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